1. Field of the Invention
The present invention relates to the field of data communications. More particularly, the present invention relates to a high level data link control ("HDLC") accelerator comprising a fully programmable CRC generation circuit, a partial data packet formatting/unformatting capability and a dual-mode register set wherein the HDLC accelerator is being controlled through status notification.
2. Background Art Related to the Invention
Over the last few decades, modems have been used to enable two remotely located sources (e.g., computer systems) to communicate with each other over standard telephone lines. Typically, a modem includes a signal processing system which formats (i.e., encodes) outgoing digital data from a local source and unformats (i.e., decodes) incoming digital data from a remote source. Normally, a conventional HDLC accelerator is implemented within the signal processing system to perform these formatting and unformatting operations in accordance with a well-known HDLC protocol referred to as "zero insertion" and "zero deletion", respectively. As a result, the conventional HDLC accelerator enables a processing unit of the computer system to execute more computationally intensive instructions instead of performing HDLC formatting and unformatting operations. Moreover, designed for performing HDLC-specific algorithmic tasks, the conventional HDLC accelerator minimizes formatting and unformatting time thereby enhancing the overall efficiency and capability of the signal processing system. Although the conventional HDLC accelerator apparently offers several advantages, it also affords a number of disadvantages.
One disadvantage is that conventional HDLC accelerators employ separate formatting and unformatting register sets. The use of separate formatting and unformatting register sets is somewhat repetitive because both register sets perform many identical operations. Thus, for a signal processing system implemented on a single integrated circuit, multiple register sets unnecessarily waste area and increase the device count i.e., the overall number of transistors, required by the HDLC accelerator. An HDLC accelerator that could both format and unformat data using the same register set is therefore desirable.
Moreover, conventional HDLC accelerators typically utilize interrupts in transmitting data to and receiving data from the processing unit. To service these interrupts, the processing unit incurs software overhead i.e., a processor executed control operation requiring the processing unit to (i) save to memory its current state before HDLC data transmission or retrieval and (ii) restore this saved state after HDLC data transmission or retrieval has completed so that the processing unit may continue its pre-HDLC operation. These interrupts adversely impact the performance of the signal processing system especially if the time required to perform the software overhead is relatively large compared to the time actually required by the HDLC formatting and unformatting operation.
In addition, due to the necessity of an interrupt scheme, the conventional HDLC accelerator employs (i) interrupt assertion circuitry which indicates a need for HDLC data transmission or retrieval and (ii) data buffer circuitry (e.g., FIFOs) which stores outgoing data until the processing unit responds to a transmit interrupt request, and incoming data when the processing unit responds to a receive interrupt request. To overcome performance degradation caused by the above-described interrupts, the data buffer circuitry provides large storage capacities. However, this further increases the device count which may diminish the number of transistors available to implement other types of circuits in the signal processing system. Thus, an HDLC accelerator which minimizes the impact to system performance and eliminates the use of both the interrupt assertion circuitry and data buffer circuitry is desirable.
Besides providing HDLC formatting and unformatting, the conventional HDLC accelerator often generates a Cyclic Redundancy Checkword ("CRC or CRC checkword") which is used to check that no errors have occurred in the HDLC data transmission or retrieval over standard telephone lines. The use of CRCs is widely known in the art, with several established standards for data communication protocols. Typically, conventional HDLC accelerators perform a CRC generation function based on a single, specific CRC generator polynomial. Such a constraint limits the number of applications which can be performed by the signal processing system. This, in turn, limits the overall flexibility and reduces marketability of the signal processing system. An HDLC accelerator which can be programmed to generate a CRC based upon any existing or yet to be created CRC generator polynomial is therefore desirable as it provides the flexibility to enter new applications or markets without redesigning CRC generation circuits.
Lastly, the conventional HDLC accelerator typically does not allow formatting and unformatting of partial data packets (i.e., bytes having &lt;8 valid bits and words having &lt;16 valid bits). This also places a constraint on the number of applications which can be performed by the signal processing system and, as a result, limits marketability. Thus, it is desirable to provide an HDLC accelerator that attains the flexibility of formatting and unformatting data packets of all valid bit enumerations.